This invention relates to the field of dynamic logic circuits. More particularly, this invention relates to techniques for protecting dynamic logic circuits from noise at the inputs.
Dynamic logic circuits are designed to operate at high speeds. They operate in two phases or cycles, a pre-charge phase or cycle and an evaluate phase or cycle. During the precharge phase or cycle, the voltage level at an output node of the dynamic logic circuit is precharged toward a high voltage level. During the evaluate phase or cycle, the voltage level at the output node is evaluated, in which case it may remain at the high level or it may be driven down toward a low voltage or ground level, depending upon the inputs to the circuit and the circuit functional design. However, dynamic logic circuits are often highly sensitive to noise at their inputs. In some dynamic logic circuits, noise at the inputs can lead to a xe2x80x9cfalse evaluatexe2x80x9d. This means the voltage at the output node may fail to fully charge due to noise at the inputs during the precharge phase before the circuit is ready to be evaluated. This could lead to false evaluate results during the evaluate phase or cycle which can affect the overall performance of the dynamic logic circuit. There are several prior art techniques for reducing noise sensitivity.
FIG. 1 illustrates a first prior art technique for reducing noise sensitivity in dynamic logic circuits. As shown in FIG. 1, a dynamic logic NAND gate is comprised of a number of transistors. A first P type transistor 102 is used to couple an output node O to a high voltage rail Vdd, in order to precharge a voltage level at the output node toward the high voltage rail Vdd when the clock signal CLK is low. This is known as the precharge phase or cycle.
Three N type transistors 103, 104 and 107 operate as a current flow or evaluate path for coupling the output node O to a low voltage or ground rail GND. During the evaluate phase or cycle, the clock signal CLK is high, which causes the first P type transistor 102 to turn off and the third N type transistor 107 to activate. Dependent upon the inputs A and B, the transistors 103 and 104 may activate during the evaluate phase or cycle, allowing current to flow from the output node O toward the low voltage or ground rail GND, thereby driving the voltage level at the output node back toward the low voltage or ground level GND.
In the prior technique for protecting the dynamic logic circuit from noise which is illustrated in FIG. 1, each input A and B into the dynamic logic circuit 101, is passed through a pair of inverters. Accordingly, the input A is passed through inverters 105a and 106a before it is coupled to the dynamic logic circuit 101. Likewise, the input B is passed through inverters 105b and 106b before it is coupled to the dynamic logic circuit 101. The use of an inverter pair for each input prevents moderate noise on either input A or B from activating the current flow or evaluate path between the output node O and the low voltage or ground rail GND before the inputs are valid. This ensures that the voltage level at the output node O is fully precharged to the high voltage level during the precharge phase or cycle.
The inverters will only allow the inputs A and B to the dynamic logic circuit 101 to trigger a discharge of current from the output node through the current flow or evaluate path if the inputs A and B are both at voltage levels above the activation levels of the inverters 105a-b and 106a-b. Therefore, the circuit 101 is not as susceptible or sensitive to noise at the inputs A and B because the two inverters in each inverter pair will not both activate when noise is present. However, use of the inverter pair at each input A and B slows down the proper operation of the dynamic logic circuit during the evaluate phase or cycle. The delay imposed through the use of a dual inverter configuration may be significant and is undesirable in most dynamic logic circuit design applications.
FIG. 2 illustrates a technique for reducing noise sensitivity in dynamic logic circuits using a NAND logic gate comprised of a number of transistors. A first P type transistor 202 is used to couple an output node O to a high voltage rail Vdd, in order to precharge a voltage level of output node O towards a high voltage rail Vdd when the clock signal CLK is low. This is known as the precharge phase or cycle.
Further, three different N type transistors 203, 204 and 207 are coupled together serially and operate as a current flow or evaluate path in order to couple the output node O of the dynamic logic circuit to a low voltage or ground rail GND. Two of the N type transistors 203 and 204 have their respective gates coupled to receive one of the two inputs A and B. The third N type transistor 207 has its gate coupled to receive the clock signal CLK.
As explained earlier, when the clock signal CLK is active, the circuit is in the evaluate phase or cycle. When this occurs, the first P type transistor 202 is turned off and the third N type transistor 207 is active. The inputs A and B may then activate the two other N type transistors 203 and 204; in which case, the voltage at the output node O will be driven toward the low voltage or ground rail GND.
In FIG. 2, the dynamic logic circuit is protected from noise at either of the inputs through the use of a pair of P type transistors 210 and 211. Each P type transistor has its source coupled to the high voltage rail Vdd and its drain coupled to the drain of one of the N type transistors (the P type transistor 210 has its drain coupled to the drain of the N type transistor 203, while the P type transistor 211 has its drain coupled to the drain of the N type transistor 204). Each P type transistor 210 and 211 has its gate coupled to receive one of the inputs A or B. The two P type transistors 210 and 211 are preferably configured to activate only when a voltage equal to or greater than one half of the voltage level at the high voltage rail Vdd is applied to the gate of either transistor. Accordingly, in one preferred embodiment, unless the inputs A and B are both at voltage levels greater than xc2xd Vdd. the voltage at the output node O remains fully charged. This protects the circuit from erroneously discharging if noise appears at either input A or B. It is understood, that the two P type transistors 210 and 211 may be adjusted to require higher turn-on or activation voltages in order to increase the level of noise protection provided.
The method for protecting against noise in dynamic circuits illustrated in FIG. 2 is more desirable than using the dual inverter design illustrated in FIG. 1 since it does not significantly delay operation of the circuit. However, this method will not work in all dynamic logic circuits. For example, this method will not work in dynamic logic OR gates or NOR gates. FIG. 3 illustrates a dynamic logic NOR gate which has no noise protection circuitry.
As shown in FIG. 3, the dynamic NOR gate 301 is comprised of a single P type transistor 305 which is coupled to three different N type transistors 306, 307 and 308 which are arranged in parallel. The P type transistor 305 has its source coupled to a high voltage source Vdd, its drain coupled to an output node O, and its gate coupled to receive a clock signal CLK as an input. The P type transistor 305 is activated whenever the clock signal CLK is low, and a voltage level at the output node O is driven toward the high voltage rail Vdd. This occurs when the NOR gate 301 is in the precharge phase or cycle.
The three different N type transistors 306, 307 and 308 are all coupled in parallel, such that each N type transistor has its drain coupled to the output node O, and its source coupled to a common node CN. The first N type transistor 306 has its gate coupled to receive an input signal A. The second N type transistor 307 has its gate coupled to receive an input signal B. The third N type transistor 308 has its gate coupled to receive an input signal C.
A fourth N type transistor 310 is coupled in series with the three different N types transistors 306, 307 and 308, between the common node CN and a low voltage or ground rail GND. The fourth N type transistor 310 has its drain coupled to the common node CN, its source coupled to the ground rail GND, and its gate coupled to receive the clock signal CLK. The fourth N type transistor 310 is active when the clock signal CLK is high or active. This occurs when the circuit is in an evaluate mode. The fourth N type transistor 310 n combination with the three different N type transistors 306, 307 and 308, forms three different current flow paths or evaluate paths from the output node O to the low voltage or ground rail GND. If either signal A, B or C is high or active during the evaluate mode, the corresponding current flow or evaluate path is activated and the voltage level at the output node O drops as current is drawn through the respective N type transistor in the three N type transistors 306, 307 and 308 and the fourth N type transistor 310 to the low voltage or ground rail GND.
If the voltage level of any of the inputs A, B, or C is high as a result of noise on that input and this noise occurs during the precharge phase or cycle, then the voltage level at the output node O may not fully charge to the appropriate high voltage level. This can lead to errors during the evaluate phase or cycle. More specifically, if there is sufficient noise at any of the inputs A, B or C, then that transistor where the noise occurs may activate, causing the current flow or evaluate path to operate during the precharge phase or cycle. This will cause current to leak from the output node O to the low voltage or ground rail GND through the respective current flow or evaluate path, thereby preventing the voltage at the output node O from fully charging to the proper high voltage level.
Unfortunately, the method of protecting the input lines which was previously discussed with reference to FIG. 2 will not work in this case. FIG. 4 illustrates the same NOR gate shown in FIG. 3; but, with the inputs A, B, and C protected in accordance with the prior art techniques discussed earlier. As shown, transistor 306 is coupled to receive input A and the input is protected using a P type transistor 315. The P type transistor 315 has its source coupled to the high voltage rail Vdd, its drain coupled to the drain of the N type transistor 306, and its gate coupled to receive the input A. The P type transistor maintains the voltage level of the output node O at a high voltage level until the NOR gate is in the evaluate phase or cycle, and unless the input A is valid. Similarly, transistor 307 is coupled to receive input B and the input is protected using a P type transistor 316. The P type transistor 316 has its source coupled to the high voltage rail Vdd, its drain coupled to the drain of the N type transistor 307, and its gate coupled to receive the input B. The P type transistor 316 maintains the voltage level of the output node O at a high voltage level until the NOR gate is in the evaluate phase or cycle, and unless the input B is valid. Finally, transistor 308 is coupled to receive input C and the input is protected using a P type transistor 317. The P type transistor 317 has its source coupled to the high voltage rail Vdd, its drain coupled to the drain of the N type transistor 308, and its gate coupled to receive the input C. The P type transistor 317 maintains the voltage level of the output node O at a high voltage level until the NOR gate is in the evaluate phase or cycle, and unless the input C is valid.
FIG. 5 shows a truth table which illustrates the problem with using the prior art technique discussed earlier. As shown in FIG. 5, if the inputs A and B are each at logic low voltage levels during the evaluate, but the input C is at a logic high voltage level, then the NOR gate should produce a logic low. However, if the inputs are protected in accordance with the prior art method discussed earlier, then the low voltage levels at the inputs A and B will actuate the P type transistors, thereby driving the voltage level at the output node toward the logic high voltage level. Additionally, in the case where only A is low and B and C are high, the output is unknown. This is because although the inputs B and C have actuated the second and third current flow path from the output node O to ground GND, the P type transistor 315 continues to try to drive the voltage level at the output node O toward the high voltage rail Vdd. Accordingly, the output voltage at the output node O will be at some unknown voltage level between the high voltage rail Vdd and the low voltage or ground rail GND. Thus, it is seen from analyzing the truth table of FIG. 5, that the prior art techniques used for reducing effects of noise at inputs in dynamic circuits will not work.
Accordingly, what is needed is an alternative method for protecting a dynamic circuit which may include logic OR gates or logic NOR gates from noise at the inputs to these gates without interfering with the proper operation of the circuit.
In accord with the present invention, a noise protection circuitry is disclosed for protecting a dynamic logic circuit having an output voltage at an output node from noise input signals to the circuit. The noise protection circuitry generally comprises: a first transistor coupled between the output node and a first current flow or evaluate path, wherein the first transistor is selectively activated by a first input signal during an evaluate phase, thereby allowing current to flow from the output node through the first current flow or evaluate path toward a low voltage or ground rail and causing the output voltage to drop; a second transistor opposite in polarity from the first transistor coupled between the first current flow or evaluate path, the first transistor, and the high voltage rail, wherein the second transistor is activated by the first input signal if the first transistor is not activated during the evaluate phase, thereby ensuring that current does not flow to the first current flow or evaluate path.